In digital-signal-transmission including digital CATV, CS digital broadcasting and the like, synchronizing signals, error-correcting codes, etc. are added to signals at the transmission side before the signals are transmitted. The synchronizing signal (hereinafter called "Sync signal"), among others, is essential for restoring the signals on a receiver side.
FIG. 7 depicts a format depicting a transmission sequence and placement of signal data in vestigial side band (VSB) transmission employed in the Advanced Television (ATV) in the U.S. A circuit for detecting this Sync signal (a segment Sync signal in this case) in digital signal transmission such as VSB transmission is illustrated as a prior art in FIG. 8. In the meantime, an interval between the adjacent Sync signals in FIG. 7 corresponds to 832 symbols.
In FIG. 8, the digital signals transmitted in the format of the VSB transmission are fed into an input terminal 100. The Sync signal included in this input digital signal "a" undergoes a pattern check section 2 where the Sync signal is checked whether its pattern is matched with the reference pattern of the synchronizing signal. In other words, this pattern check section 2 checks a signal pattern included in the segment Sync signal (corresponding to 4 symbols) with the predetermined reference pattern (corresponding to 4 symbols), and when they agree with each other, the pattern check section 2 outputs a high level signal "b". This output signal from the pattern check section 2 is fed into an agreement detection counter 3, disagreement detection counter 4 and Sync counter 6.
The agreement detection counter 3 counts how many signal patterns agree with the reference pattern in the pattern check section 2. In other words, when a timing signal "c" from the Sync counter 6 is fed into the agreement detection counter 3, which counts up one by one provided the output signal "b" from the pattern check section 2 is on a high level. When the count value reaches to "3", the counter 3 does not count up any more and stays at "3" even if the output signal "b" is at the high level. When the output signal "c" is fed into the counter 3, which is reset to "0" provided the output signal "b" from the pattern check section 2 is at a low level.
When the disagreement detection counter 4 receives the timing signal "c" from the Sync counter 6, it counts up one by one provided the output signal "b" from the pattern check section 2 is at the low level. When the counted value reaches to "3", the counter 4 does not count up any more and stays at "3" even if the output signal "b" is at the low level. When the output signal "c" is fed into the counter 4, the counter is reset to "0" provided the output signal "b" from the pattern check section 2 is at the high level.
A Sync detection determination section 5 determines a Sync detection based on the output signals from the counters 3 and 4. Namely, it outputs a high level signal "f" indicating a Sync detected status just when an output signal "e" from the counter 4 is changed to "0" while an output signal "d" from the counter 3 stays at "3". On the other hand, it outputs a low level signal "f" indicating a Sync non-detected status just when the output signal "e" from the counter 4 changes to "3" while the output signal "d" from the counter 3 is "0".
A necessary number of input Sync signals can be changed by resetting the count set values of the counters 3 and 4 as well as the set value of the Sync detection determination section 5.
The Sync counter 6 outputs a signal "c" that controls timings of the count operations of the counters 3 and 4 by using the output signal "b" from the pattern check section 2 and the output signal "f" from the Sync detection determination section 5. Namely, the Sync counter 6 starts counting whenever it receives the output signal "b", when the output signal "f" is on a low level indicating the Sync non-detected status, and the counter 6 outputs the timing signals "c" for a period of 4 symbols every time after a lapse of the period corresponding to one segment (equal to 832 symbols.)
When the output signal "f" is on a high level indicating the Sync detected status, the Sync counter 6 starts counting just when the output signal "f" changes to the high level, and then outputs a high level timing signals "c" for the period of 4 symbols every time after the lapse of the period corresponding to one segment (equal to 832 symbols.) While, when the output signal "f" is on a low level, the Sync counter 6 does not output the timing signal "c" as long as the one segment period is still active, even the output signal "b" is given before the period of one segment is lapsed.
An operation of the Sync signal detection circuit is described hereinafter by referring to the timing charts in FIGS. 9 and 10.
FIG. 9 depicts an initial stage where a digital signal is just fed through the input terminal 100. A digital signal "a" (equal to an input signal (a) in FIG. 9) fed into the input terminal 100 shown in FIG. 8 is firstly sent to the pattern check section 2. The pattern check section 2 detects a place where the pattern of the segment Sync signal shown in FIG. 7 exists, and outputs the high level signals "b" [equal to (b) in FIG. 9] indicating a pattern agreement as well as corresponding to 4 symbols to the agreement detection counter 3, disagreement detection counter 4 and Sync counter 6 when the pattern of the segment Sync signal agrees with the reference pattern.
The above counters 3 and 4 count responding to the output signals "b" and the timing signals "c", and then output resulting signals "d" and "e" (equal to (d) and (e) in FIG. 9) to the Sync detection determination section 5.
In the case of FIG. 9, when the counter 3 receives the timing signal "c", the output signal "b" from the pattern check section 2 is on a high level, the counter 3 thus counts up by one; however, when the count value reaches to "3", the counter does not count up any more and keeps "3" (refer to (d) in FIG. 9).
On the other hand, when the counter 4 receives the output signal "c" from the Sync counter 6, the counter 4 is reset to "0" provided the output signal "b" stays at the high level [refer to (e) in FIG. 9].
The Sync detection determination section 5 determines a detection of a Sync signal by using the count values given from the counters 3 and 4. Namely, the section 5 shown in FIG. 8 outputs a high level signal "f" (refer to (f) in FIG. 9) indicating the Sync. detected status just when (at the timing "ta") the output signal "e" from the counter 4 changes to "0" while the output signal "d" is "3".
As such, when the Sync. detection determination section 5 outputs a high level signal "f" that indicates a status of detecting a Sync signal, a data area shown in FIG. 7 is correctly located. The data included in this data area thus undergo various processes in data process circuit (not shown in FIG. 8) afterward.
In the case shown in FIG. 9, the Sync counter 6 outputs high level timing signals "c" to the counters 3 and 4 for the period of 4 symbols every time after a lapse of the period corresponding to one segment (equal to 832 symbols) since the time at the point "ta" (refer to (f) in FIG. 9) when the output signal "f" changes from the low level (Sync. non-detected status) to the high level (Sync. detected status).
FIG. 10 depicts a case where a digital signal is fed through the input terminal 100 (refer to FIG. 8), and another digital signal takes over the signal, though on the way, due to, e.g., switching a receiver (time: "t0". ) In this case, the Sync detected status is thus temporarily changed to the Sync non-detected status due to the switch-over. The determination section 5 afterward shows the Sync detected status again.
In other words, before the signal is switched over (before "t0" in FIG. 10), the determination section 5 outputs high level signals "f" indicating the "Sync detected status" (refer to (f) in FIG. 10). Since the time when the signal "f" has turned to the high level indicating the Sync detected status, the Sync counter 6 thus continuously outputs the high level timing signals "c" (refer to (c) in FIG. 10) for the period of 4 symbols every time after the lapse of one segment period (=832 symbols) to the counters 3 and 4. Under this condition, the count values of counters 3 and 4 are "3" and "0" respectively (refer to (d) and (e) in FIG. 10.)
Based on this status, another input signal takes over the present input signal at the time "t0". The phases of both these input signals seldom coincide with each other, and rather they do not coincide in general, therefore, the output period of the signal "b" from the pattern check section 2 becomes longer or shorter than the one segment period (=832 symbols) (refer to (b) in FIG. 10.) The output signal "b" from the section 2 is, therefore, at a low level when the Sync counter 6 outputs the timing signal "c" (=t0). The agreement detection counter 3 is thus reset (refer to (d) in FIG. 10). On the other hand, the disagreement detection counter 4 counts up one by one every time when receiving the timing signal "c". When the count value reaches to "3", the counter 4 does not count up anymore and keeps the value at "3" (refer to (e) in FIG. 10.)
The Sync detection determination section 5 outputs the low level signal "f" indicating the Sync. non-detected status just when (time=t2) the output signal "e" from the counter 4 changes to "3" while the output signal "d" from the counter 3 is "0" (refer to (f) in FIG. 10.)
When the signal "f" changes from the high level to low level (i.e., from the Sync detected status to Sync. non-detected status), the Sync counter 6 outputs the high level timing signals "c" sequentially to the counters 3 and 4 for the period of 4 symbols every time after the lapse of one segment period (=832 symbols) from each rising point of the input signal "b" fed from the pattern check section 2. For instance, the timing signal "c" at the time=t3 is produced after one segment period (=832 symbols) of the output signal "b" produced at the time=t2' tapped off from the pattern check section 2, because the output signal "f" tapped off from the determination section 5 is on a low level (refer to (b) and (c) in FIG. 10).
In the Sync non-detected status, when the counters 3 and 4 receive the timing signals (c) tapped off from the Sync counter 6, the agreement counter 3 counts up by one if the output signal "b" is at a high level (time=t3) and the disagreement counter 4 is reset to "0". After this, the counter 3 counts up one by one at time=t4 and t5 (refer to (d) in FIG. 10.) When the count value of the counter 3 reaches to "3" while the output signal "e" from the counter 4 is "0" (time=t5), the determination section 5 outputs again the high level signal "f" indicating the Sync detected status.
As shown in FIG. 10, when a digital signal fed through the input terminal 100 is switched over, though on the way of transmission, to another input digital signal by switching a receiver, the segment Sync signal must be given twice (at the time=t0' and t1') until the Sync detected status is turned temporarily to the Sync non-detected status by this signal switch. Further, the segment Sync signal must be given in four times (time=t2', t3, t4 and t5) before the Sync non-detected status is restored to the Sync detected status. In other words, the segment Sync signal must be given in six times between switching the signal and restoring to the Sync detected status.
This arrangement gives a protective function to Sync signal detecting systems, for a lack of a Sync signal due to noises or a lack of data causes malfunction, and the same pattern as a Sync signal comes into a data area by chance also causes malfunction. This arrangement can thus prevent the malfunction.
The above status is described by referring to the timing charts of FIGS. 11 and 12. FIG. 11 depicts a status where disturbance from outside such as noises deforms the pattern of a Sync signal included in an input signal "a" when the circuit is Sync detected status (=the agreement detection counter 3 indicates "3" and the disagreement detection counter 4 indicates "0" while the Sync detection determination section 5 outputs a high level signal "f" indicating the Sync detection status.)
At this time (=t b1), the pattern check section 2 does not output a high level signal pulse indicating a pattern agreement, and stays outputting a low level signal. In this case, when the Sync counter 6 outputs the timing signal "c", the agreement counter 3 is reset to "0", and the disagreement counter 4 indicates "1" on the other hand.
However, these disturbances such as noises and the like occur suddenly and do not last. Therefore, assume all the Sync signals given after the time=t b2 have the normal patterns, the pattern check section 2 would output the high level pulse signal "b" indicating the Sync detected status, the agreement counter 3 thus counts up one by one while the disagreement counter 4 is reset to "0".
Since the Sync detection determination section 5 outputs the low level signal indicating the Sync non-detected status under the condition that the counter 3 taps off the output signal "d" (=0) and the counter 4 taps off the output signal "e" (=3), the determination section 5 does not change immediately to the low level indicating the Sync non-detected status when the Sync signal is distorted temporarily, as shown in FIG. 11, due to the disturbance. Rather, the section 5 still holds the high level indicating the Sync detected status, thus the malfunction is prevented.
FIG. 12 depicts the following case; As shown in FIG. 10, a signal is switched over to another signal, and the counter 3 thus indicates "0" while the counter 4 indicates "3" (time=t c0). The section 5 is ready to output the low level signal indicating the Sync non-detected status. Then, a pattern same as that of the Sync signal abruptly appears in the data area at the time=t c1, .
At this time (=t c1), the pattern check section 2 outputs the high level signal "b" indicating the pattern agreement, and the Sync counter 6 outputs the timing signal "c" at the time=t c2 responding to the signal "b" after the lapse of one segment period (=832 symbols). Between t c1 and t c2, the section 2 supplies the signal "b" to the counter 6; however, the counter 6 neglects these signal "b" as described previously.
When the Sync counter 6 outputs the timing signal "c" at the time=t c2, the output signal "b" from the pattern check section 2 is at a low level. Although the agreement detection counter 3 indicates "0" while the disagreement detection counter 4 indicates "3", the Sync detection determination section 5 keeps outputting the low level signal "f" indicating the Sync non-detection status.
In other words, when a pattern same as that of the Sync signal appears abruptly in the data area, the determination section 5 does not indicate Sync detected status but stays at the low level indicating Sync non-detected status, thus the malfunction is prevented.
The conventional Sync signal detection circuit indeed prevents malfunctions against the lack of Sync signal due to noises and lack of data, as well as the same pattern as the Sync pattern appears in the data area by chance, but this preventive function works unconditionally even when an input signal is simply switched over as described above. Therefore, as shown in FIG. 10, the Sync signal must be given as many as 6 times from the signal switch-over until the Sync detected status is indicated again, which delays detecting a Sync signal.